1. Technical Field
The present invention generally relates to a boost circuit and in particular to a boost circuit that generates an adjustable boost voltage.
2. Description of the Related Art
In integrated circuit design, the trend has been to reduce a supply voltage level for integrated circuits (chips) in order to reduce leakage currents. However, reducing a supply voltage level may result in suboptimal performance for certain circuits within a chip. For example, a supply voltage level is a limiting performance factor for wordline driver circuits (wordline drivers) of complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM). In general, using higher wordline driver circuit voltage levels decreases wordline resistor-capacitor (RC) delay and decreases an on-resistance (Ron) of SRAM passgates. Unfortunately, increasing a global supply voltage level for an SRAM (according to one conventional approach) leads to significantly increased power consumption, even for non-critical circuits in the SRAM. Moreover, implementing multiple different global supply voltages according to another conventional approach leads to increased complexity of power wiring and chip voltage regulation. In general, while both conventional approaches provide a same supply voltage to all memory arrays in a chip, individual macro tuning cannot be achieved with the conventional approaches.
With reference to FIG. 1, U.S. Patent Application Publication No. 2008/0068902 (hereinafter “the '902 publication”) discloses a wordline boost circuit 100 that employs a capacitor CB that is charged (by turning switches S3 and S2 on) to a supply voltage VDD level. The voltage on capacitor CB is then stacked onto the supply voltage VDD (by turning switch S1 on and by turning switches S2 and S3 off) when a boost voltage VB is desired (i.e., when a memory access is performed via wordline driver circuit 102, as indicated when a wordline (WL) pulse signal is generated). As is illustrated, switches S1 and S2 are included within inverter I1. In theory, during the voltage boost, wordline drivers are supplied with 2 VDD (which may violate an allowed gate-to-source voltage (Vgs) of a p-channel metal-oxide semiconductor field-effect transistor (MOSFET) of wordline driver circuit 102). In practice, the boost voltage on a wordline depends on a value of the supply voltage VDD, a wordline capacitance value, a value of capacitor CB, and an on-resistance of switch S1, among other parameters. Moreover, in wordline boost circuit 100, a level of the boost voltage VB is not readily ascertainable and is not adjustable (to meet specific system requirements).